? semiconductor components industries, llc, 2014 august, 2014 ? rev. 10 1 publication order number: mc14024b/d mc14024b 7-stage ripple counter the mc14024b is a 7?stage ripple counter with short propagation delays and high maximum clock rates. the reset input has standard noise immunity, however the cl ock input has increased noise immunity due to hysteresis. the output of each counter stage is buffered. features ? diode protection on all inputs ? output transitions occur on the falling edge of the clock pulse ? supply voltage range = 3.0 vdc to 18 vdc ? capable of driving two low?power ttl loads or one low?power schottky ttl load over the rated temperature range ? pin?for?pin replacement for cd4024b ? nlv prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable ? this device is pb?free and is rohs compliant maximum ratings (voltages referenced to v ss ) symbol parameter value unit v dd dc supply voltage range ?0.5 to +18.0 v v in , v out input or output voltage range (dc or transient) ?0.5 to v dd + 0.5 v i in , i out input or output current (dc or transient) per pin 10 ma p d power dissipation, per package (note 1) 500 mw t a ambient temperature range ?55 to +125 c t stg storage temperature range ?65 to +150 c t l lead temperature (8?second soldering) 260 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. temperature derating: ?d/dw? packages: ?7.0 mw/ c from 65 c to 125 c this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high?impedance circuit. for proper operation, v in and v out should be constrained to the range v ss (v in or v out ) v dd . unused inputs must always be tied to an appropriate logic voltage level (e.g., either v ss or v dd ). unused outputs must be left open. http://onsemi.com marking diagram soic?14 d suffix case 751a 1 14 14024bg awlyww a = assembly location wl, l = wafer lot yy, y = year ww, w = work week g = pb?free package see detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. ordering information 11 12 13 14 8 9 10 5 4 3 2 1 7 6 nc q2 q1 nc v dd nc q3 q6 q7 reset clock v ss q4 q5 pin assignment v dd = pin 14 v ss = pin 7 nc = no connection
mc14024b http://onsemi.com 2 truth table clock reset state 0 0 no change 0 1 all outputs low 1 0 no change 1 1 all outputs low 0 no change 1 all outputs low 0 advance one count 1 all outputs low logic diagram clock reset 2 1 12 q1 11 q2 4 q6 3 q7 q3 = pin 9 q4 = pin 6 q5 = pin 5 cq rq cq rq cq rq cq rq ordering information device package shipping ? mc14024bdg soic?14 (pb?free) 55 units / rail nlv14024bdg* soic?14 (pb?free) 55 units / rail mc14024bdr2g soic?14 (pb?free) 2500 / tape & reel NLV14024BDR2G* soic?14 (pb?free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *nlv prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable.
mc14024b http://onsemi.com 3 ????????????????????????????????? ????????????????????????????????? (voltages referenced to v ss ) characteristic symbo l v dd vdc ?55 c 25 c 125 c unit min max min typ (note 2) max min max output voltage ?0? leve l v in = v dd or 0 v in = 0 or v dd ?1? leve l v ol 5.0 10 15 ? ? ? 0.05 0.05 0.05 ? ? ? 0 0 0 0.05 0.05 0.05 ? ? ? 0.05 0.05 0.05 vdc v oh 5.0 10 15 4.95 9.95 14.95 ? ? ? 4.95 9.95 14.95 5.0 10 15 ? ? ? 4.95 9.95 14.95 ? ? ? vdc input voltage ?0? leve l (v o = 4.5 or 0.5 vdc) (v o = 9.0 or 1.0 vdc) (v o = 13.5 or 1.5 vdc) (v o = 0.5 or 4.5 vdc) ?1? leve l (v o = 1.0 or 9.0 vdc) (v o = 1.5 or 13.5 vdc) v il 5.0 10 15 ? ? ? 1.5 3.0 4.0 ? ? ? 2.25 4.50 6.75 1.5 3.0 4.0 ? ? ? 1.5 3.0 4.0 vdc v ih 5.0 10 15 3.5 7.0 11 ? ? ? 3.5 7.0 11 2.75 5.50 8.25 ? ? ? 3.5 7.0 11 ? ? ? vdc output drive current (v oh = 2.5 vdc) source (v oh = 4.6 vdc) (v oh = 9.5 vdc) (v oh = 13.5 vdc) (v ol = 0.4 vdc) sin k (v ol = 0.5 vdc) (v ol = 1.5 vdc) i oh 5.0 5.0 10 15 ?3.0 ?0.64 ?1.6 ?4.2 ? ? ? ? ?2.4 ?0.51 ?1.3 ?3.4 ?4.2 ?0.88 ?2.25 ?8.8 ? ? ? ? ?1.7 ?0.36 ?0.9 ?2.4 ? ? ? ? madc i ol 5.0 10 15 0.64 1.6 4.2 ? ? ? 0.51 1.3 3.4 0.88 2.25 8.8 ? ? ? 0.36 0.9 2.4 ? ? ? madc input current i in 15 ? 0.1 ? 0.00001 0.1 ? 1.0 adc input capacitance (v in = 0) c in ? ? ? ? 5.0 7.5 ? ? pf quiescent current (per package) i dd 5.0 10 15 ? ? ? 5.0 10 20 ? ? ? 0.005 0.010 0.015 5.0 10 20 ? ? ? 150 300 600 adc total supply current (notes 3 & 4) (dynamic plus quiescent, per package) (c l = 50 pf on all outputs, all buffers switching) i t 5.0 10 15 i t = (0.31 a/khz) f + i dd i t = (0.60 a/khz) f + i dd i t = (1.89 a/khz) f + i dd adc product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 2. data labelled ?typ? is not to be used for design purposes but is intended as an indication of the ic?s potential performance. 3. the formulas given are for the typical characteristics only at 25 c. 4. to calculate total supply current at loads other than 50 pf: i t (c l ) = i t (50 pf) + (c l ? 50) vfk where: i t is in a (per package), c l in pf, v = (v dd ? v ss ) in volts, f in khz is input frequency, and k = 0.001.
mc14024b http://onsemi.com 4 switching characteristics (note 5) (c l = 50 pf, t a = 25 c) characteristic symbol v dd min typ (note 6) max unit output rise and fall time t tlh , t thl = (1.5 ns/pf) c l + 25 ns t tlh , t thl = (0.75 ns/pf) c l + 12.5 ns t tlh , t thl = (0.55 ns/pf) c l + 9.5 ns t tlh , t thl 5.0 10 15 ? ? ? 100 50 40 200 100 80 ns propagation delay time clock to q1 t plh , t phl = (1.7 ns/pf) c l + 295 ns t plh , t phl = (0.66 ns/pf) c l + 117 ns t plh , t phl = (0.5 ns/pf) c l + 85 ns clock to q7 t plh , t phl = (1.7 ns/pf) c l + 915 ns t plh , t phl = (0.66 ns/pf) c l + 367 ns t plh , t phl = (0.5 ns/pf) c l + 275 ns reset to q n t plh , t phl = (1.7 ns/pf) c l + 415 ns t plh , t phl = (0.66 ns/pf) c l + 217 ns t plh , t phl = (0.5 ns/pf) c l + 155 ns t plh , t phl 5.0 10 15 5.0 10 15 5.0 10 15 ? ? ? ? ? ? ? ? ? 380 150 110 1000 400 300 500 250 180 600 230 175 2000 750 565 800 400 300 ns clock pulse width t wh 5.0 10 15 500 165 125 200 60 40 ? ? ? ns reset pulse width t wh 5.0 10 15 600 350 260 375 200 150 ? ? ? ns reset removal time t rem 5.0 10 15 625 190 145 250 75 50 ? ? ? ns clock input rise and fall time t tlh , t thl 5.0 10 15 ? ? ? ? ? ? 1.0 8.0 200 s ms s input pulse frequency f cl 5.0 10 15 ? ? ? 2.5 8.0 12 1.0 3.0 4.0 mhz 5. the formulas given are for the typical characteristics only at 25 c. 6. data labelled ?typ? is not to be used for design purposes but is intended as an indication of the ic?s potential performance.
mc14024b http://onsemi.com 5 external power supply external power supply figure 1. typical output source characteristics test circuit figure 2. typical output sink characteristics test circuit v dd v dd v ss i oh v ol = v out c r q n count q n to a logic 1" level. v dd v oh = v out v ss i ol c r q n figure 3. power dissipation test circuit v dd 500 f 0.01 f ceramic pulse generator f c rq7 q6 q5 q4 q3 q2 q1 v ss i d c l c l c l c l c l c l c l
mc14024b http://onsemi.com 6 figure 4. functional waveforms clock (1) reset (2) q1 (12) q2 (11) q3 (9) q4 (6) q5 (5) q6 (4) q7 (3) t wl t wh t rem t plh1 t tlh t tlh t tlh t tlh t tlh t tlh t tlh t phl1 t plh2 t phl2 t phl3 t phl4 t phl5 t phl6 t phl7 t plh3 t plh4 t plh5 t plh6 t plh7 50% 50% 50% 50% 50% 50% 50% 50% 90% 90% 10% 10% 10% 90% t thl t thl t thl t thl t thl t thl t thl t r1 t r2 t r3 t r4 t r5 t r6 t r7 v dd 1 2 4 8 16 32 64 128 255 v ss v dd v ss v oh v oh v oh v oh v oh v oh v oh v ol v ol v ol v ol v ol v ol v ol input t and t = 20 ns tlh thl
mc14024b http://onsemi.com 7 package dimensions soic?14 nb case 751a?03 issue k notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b does not include dambar protrusion. allowable protrusion shall be 0.13 total in excess of at maximum material condition. 4. dimensions d and e do not include mold protrusions. 5. maximum mold protrusion 0.15 per side. h 14 8 7 1 m 0.25 b m c h x 45 seating plane a1 a m s a m 0.25 b s c b 13x b a e d e detail a l a3 detail a dim min max min max inches millimeters d 8.55 8.75 0.337 0.344 e 3.80 4.00 0.150 0.157 a 1.35 1.75 0.054 0.068 b 0.35 0.49 0.014 0.019 l 0.40 1.25 0.016 0.049 e 1.27 bsc 0.050 bsc a3 0.19 0.25 0.008 0.010 a1 0.10 0.25 0.004 0.010 m 0 7 0 7 h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.019 6.50 14x 0.58 14x 1.18 1.27 dimensions: millimeters 1 pitch soldering footprint* *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemni fy and hold scillc and its officers, em ployees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 mc14024b/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative
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